<Comment>--------------------------------------------------------------------------------</Comment><br/>
<Comment>-- light52_muldiv.vhdl -- Simple multiplier/divider module.</Comment><br/>
<Comment>--------------------------------------------------------------------------------</Comment><br/>
<Comment>-- The 8051 mul and div instructions are both unsigned and operands are 8 bit.</Comment><br/>
<Comment>--</Comment><br/>
<Comment>-- This module implements the division as a sequential state machine which takes</Comment><br/>
<Comment>-- 8 cycles to complete. </Comment><br/>
<Comment>-- The multiplier can be implemented as sequential or as combinational, in which</Comment><br/>
<Comment>-- case it will use a DSP block in those architectures that support it.</Comment><br/>
<Comment>-- No attempt has been made to make this module generic or reusable.</Comment><br/>
<Comment>--</Comment><br/>
<Comment>-- If you want a combinational multiplier but don't want to waste a DSP block </Comment><br/>
<Comment>-- in this module, you need to modify this file adding whatever synthesis </Comment><br/>
<Comment>-- pragmas your tool of choice needs.</Comment><br/>
<Comment>--</Comment><br/>
<Comment>-- Note that unlike the division state machine, the combinational product logic</Comment><br/>
<Comment>-- is always operating: when SEQUENTIAL_MULTIPLIER=true, prod_out equals </Comment><br/>
<Comment>-- data_a * data_b with a latency of 1 clock cycle, and mul_ready is hardwired</Comment><br/>
<Comment>-- to '1'.</Comment><br/>
<Comment>--</Comment><br/>
<Comment>-- FIXME explain division algorithm.</Comment><br/>
<Comment>--------------------------------------------------------------------------------</Comment><br/>
<Comment>-- GENERICS:</Comment><br/>
<Comment>-- </Comment><br/>
<Comment>-- SEQUENTIAL_MULTIPLIER        -- Sequential vs. combinational multiplier.</Comment><br/>
<Comment>--  When true, a sequential implementation will be used for the multiplier, </Comment><br/>
<Comment>--  which will usually save a lot of logic or a dedicated multiplier.</Comment><br/>
<Comment>--  When false, a combinational registered multiplier will be used.</Comment><br/>
<Comment>--</Comment><br/>
<Comment>--------------------------------------------------------------------------------</Comment><br/>
<Comment>-- INTERFACE SIGNALS:</Comment><br/>
<Comment>--</Comment><br/>
<Comment>-- clk :            Clock, active rising edge.</Comment><br/>
<Comment>-- reset :          Synchronous reset. Clears only the control registers not</Comment><br/>
<Comment>--                  visible to the programmer -- not the output registers.</Comment><br/>
<Comment>-- </Comment><br/>
<Comment>-- data_a :         Numerator input, should be connected to the ACC register.</Comment><br/>
<Comment>-- data_b :         Denominator input, should be connected to the B register.</Comment><br/>
<Comment>-- start :          Assert for 1 cycle to start the division state machine</Comment><br/>
<Comment>--                  (and the product if SEQUENTIAL_MULTIPLIER=true);</Comment><br/>
<Comment>-- </Comment><br/>
<Comment>-- prod_out :       Product output, valid only when mul_ready='1'.</Comment><br/>
<Comment>-- quot_out :       Quotient output, valid only when div_ready='1'.</Comment><br/>
<Comment>-- rem_out :        Remainder output, valid only when div_ready='1'.</Comment><br/>
<Comment>-- div_ov_out :     Division overflow flag, valid only when div_ready='1'.</Comment><br/>
<Comment>-- mul_ov_out :     Product overflow flag, valid only when mul_ready='1'.</Comment><br/>
<Comment>-- </Comment><br/>
<Comment>-- mul_ready :      Asserted permanently if SEQUENTIAL_MULTIPLIER=false.</Comment><br/>
<Comment>-- div_ready :      Deasserted the cycle after start is asserted.</Comment><br/>
<Comment>--                  Asserted when the division has completed.</Comment><br/>
<Comment>--</Comment><br/>
<Comment>--------------------------------------------------------------------------------</Comment><br/>
<Comment>-- Copyright (C) 2012 Jose A. Ruiz</Comment><br/>
<Comment>--                                                              </Comment><br/>
<Comment>-- This source file may be used and distributed without         </Comment><br/>
<Comment>-- restriction provided that this copyright statement is not    </Comment><br/>
<Comment>-- removed from the file and that any derivative work contains  </Comment><br/>
<Comment>-- the original copyright notice and the associated disclaimer. </Comment><br/>
<Comment>--                                                              </Comment><br/>
<Comment>-- This source file is free software; you can redistribute it   </Comment><br/>
<Comment>-- and/or modify it under the terms of the GNU Lesser General   </Comment><br/>
<Comment>-- Public License as published by the Free Software Foundation; </Comment><br/>
<Comment>-- either version 2.1 of the License, or (at your option) any   </Comment><br/>
<Comment>-- later version.                                               </Comment><br/>
<Comment>--                                                              </Comment><br/>
<Comment>-- This source is distributed in the hope that it will be       </Comment><br/>
<Comment>-- useful, but WITHOUT ANY WARRANTY; without even the implied   </Comment><br/>
<Comment>-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      </Comment><br/>
<Comment>-- PURPOSE.  See the GNU Lesser General Public License for more </Comment><br/>
<Comment>-- details.                                                     </Comment><br/>
<Comment>--                                                              </Comment><br/>
<Comment>-- You should have received a copy of the GNU Lesser General    </Comment><br/>
<Comment>-- Public License along with this source; if not, download it   </Comment><br/>
<Comment>-- from http://www.opencores.org/lgpl.shtml</Comment><br/>
<Comment>--------------------------------------------------------------------------------</Comment><br/>
<dsNormal></dsNormal><br/>
<Keyword>library</Keyword><Normal Text> ieee;</Normal Text><br/>
<Keyword>use</Keyword><Normal Text> ieee</Normal Text><Operator>.</Operator><Normal Text>std_logic_1164</Normal Text><Operator>.</Operator><Normal Text>all;</Normal Text><br/>
<Keyword>use</Keyword><Normal Text> ieee</Normal Text><Operator>.</Operator><Normal Text>numeric_std</Normal Text><Operator>.</Operator><Normal Text>all;</Normal Text><br/>
<dsNormal></dsNormal><br/>
<Keyword>use</Keyword><Normal Text> work</Normal Text><Operator>.</Operator><Normal Text>light52_pkg</Normal Text><Operator>.</Operator><Normal Text>all;</Normal Text><br/>
<Keyword>use</Keyword><Normal Text> work</Normal Text><Operator>.</Operator><Normal Text>light52_ucode_pkg</Normal Text><Operator>.</Operator><Normal Text>all;</Normal Text><br/>
<dsNormal></dsNormal><br/>
<Control>entity</Control><Normal Text> </Normal Text><Name>light52_muldiv</Name><Normal Text> </Normal Text><Keyword>is</Keyword><br/>
<Normal Text>    </Normal Text><Control>generic</Control><Normal Text> (</Normal Text><br/>
<Normal Text>        SEQUENTIAL_MULTIPLIER </Normal Text><Operator>:</Operator><Normal Text> </Normal Text><Data Type>boolean</Data Type><Normal Text> </Normal Text><Operator>:=</Operator><Normal Text> false</Normal Text><br/>
<Normal Text>    );</Normal Text><br/>
<Normal Text>    </Normal Text><Control>port</Control><Normal Text>(</Normal Text><br/>
<Normal Text>        clk </Normal Text><Operator>:</Operator><Normal Text>                   </Normal Text><Keyword>in</Keyword><Normal Text> </Normal Text><Data Type>std_logic</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text>        reset </Normal Text><Operator>:</Operator><Normal Text>                 </Normal Text><Keyword>in</Keyword><Normal Text> </Normal Text><Data Type>std_logic</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text>        </Normal Text><br/>
<Normal Text>        data_a </Normal Text><Operator>:</Operator><Normal Text>                </Normal Text><Keyword>in</Keyword><Normal Text> t_byte;</Normal Text><br/>
<Normal Text>        data_b </Normal Text><Operator>:</Operator><Normal Text>                </Normal Text><Keyword>in</Keyword><Normal Text> t_byte;</Normal Text><br/>
<Normal Text>        start </Normal Text><Operator>:</Operator><Normal Text>                 </Normal Text><Keyword>in</Keyword><Normal Text> </Normal Text><Data Type>std_logic</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text>        </Normal Text><br/>
<Normal Text>        prod_out </Normal Text><Operator>:</Operator><Normal Text>              </Normal Text><Keyword>out</Keyword><Normal Text> t_word;</Normal Text><br/>
<Normal Text>        quot_out </Normal Text><Operator>:</Operator><Normal Text>              </Normal Text><Keyword>out</Keyword><Normal Text> t_byte;</Normal Text><br/>
<Normal Text>        rem_out </Normal Text><Operator>:</Operator><Normal Text>               </Normal Text><Keyword>out</Keyword><Normal Text> t_byte;</Normal Text><br/>
<Normal Text>        div_ov_out </Normal Text><Operator>:</Operator><Normal Text>            </Normal Text><Keyword>out</Keyword><Normal Text> </Normal Text><Data Type>std_logic</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text>        mul_ov_out </Normal Text><Operator>:</Operator><Normal Text>            </Normal Text><Keyword>out</Keyword><Normal Text> </Normal Text><Data Type>std_logic</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text>        </Normal Text><br/>
<Normal Text>        mul_ready </Normal Text><Operator>:</Operator><Normal Text>             </Normal Text><Keyword>out</Keyword><Normal Text> </Normal Text><Data Type>std_logic</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text>        div_ready </Normal Text><Operator>:</Operator><Normal Text>             </Normal Text><Keyword>out</Keyword><Normal Text> </Normal Text><Data Type>std_logic</Data Type><br/>
<Normal Text>    );</Normal Text><br/>
<Control>end entity light52_muldiv;</Control><br/>
<dsNormal></dsNormal><br/>
<Control>architecture</Control><Normal Text> </Normal Text><Name>sequential</Name><Normal Text> </Normal Text><Keyword>of</Keyword><Normal Text> </Normal Text><Reference>light52_muldiv</Reference><Normal Text> </Normal Text><Keyword>is</Keyword><br/>
<dsNormal></dsNormal><br/>
<Signal>signal</Signal><Normal Text> bit_ctr </Normal Text><Operator>:</Operator><Normal Text>            </Normal Text><Data Type>integer</Data Type><Normal Text> </Normal Text><Keyword>range</Keyword><Normal Text> </Normal Text><Integer>0</Integer><Normal Text> </Normal Text><Range>to</Range><Normal Text> </Normal Text><Integer>8</Integer><Normal Text>;</Normal Text><br/>
<dsNormal></dsNormal><br/>
<Signal>signal</Signal><Normal Text> b_shift_reg </Normal Text><Operator>:</Operator><Normal Text>        t_word;</Normal Text><br/>
<dsNormal></dsNormal><br/>
<Signal>signal</Signal><Normal Text> den_ge_256 </Normal Text><Operator>:</Operator><Normal Text>         </Normal Text><Data Type>std_logic</Data Type><Normal Text>;</Normal Text><br/>
<Signal>signal</Signal><Normal Text> num_ge_den </Normal Text><Operator>:</Operator><Normal Text>         </Normal Text><Data Type>std_logic</Data Type><Normal Text>;</Normal Text><br/>
<Signal>signal</Signal><Normal Text> sub_num </Normal Text><Operator>:</Operator><Normal Text>            </Normal Text><Data Type>std_logic</Data Type><Normal Text>;</Normal Text><br/>
<dsNormal></dsNormal><br/>
<Signal>signal</Signal><Normal Text> denominator </Normal Text><Operator>:</Operator><Normal Text>        t_byte;</Normal Text><br/>
<Signal>signal</Signal><Normal Text> rem_reg </Normal Text><Operator>:</Operator><Normal Text>            t_byte;</Normal Text><br/>
<Signal>signal</Signal><Normal Text> quot_reg </Normal Text><Operator>:</Operator><Normal Text>           t_byte;</Normal Text><br/>
<Signal>signal</Signal><Normal Text> prod_reg </Normal Text><Operator>:</Operator><Normal Text>           t_word;</Normal Text><br/>
<Signal>signal</Signal><Normal Text> ready </Normal Text><Operator>:</Operator><Normal Text>              </Normal Text><Data Type>std_logic</Data Type><Normal Text>;</Normal Text><br/>
<dsNormal></dsNormal><br/>
<Signal>signal</Signal><Normal Text> load_regs </Normal Text><Operator>:</Operator><Normal Text>          </Normal Text><Data Type>std_logic</Data Type><Normal Text>;</Normal Text><br/>
<dsNormal></dsNormal><br/>
<Control>begin</Control><br/>
<dsNormal></dsNormal><br/>
<Comment>-- Control logic ---------------------------------------------------------------</Comment><br/>
<dsNormal></dsNormal><br/>
<Name>control_counter</Name><Operator>:</Operator><Normal Text> </Normal Text><Process>process</Process><Normal Text>(clk)</Normal Text><br/>
<Process>begin</Process><br/>
<Normal Text>    </Normal Text><Control>if</Control><Normal Text> clk</Normal Text><Attribute>'event</Attribute><Normal Text> </Normal Text><Keyword>and</Keyword><Normal Text> clk</Normal Text><Operator>=</Operator><Attribute>'1'</Attribute><Normal Text> </Normal Text><Control>then</Control><br/>
<Normal Text>        </Normal Text><Control>if</Control><Normal Text> reset</Normal Text><Operator>=</Operator><Attribute>'1'</Attribute><Normal Text> </Normal Text><Control>then</Control><br/>
<Normal Text>            bit_ctr </Normal Text><Operator><=</Operator><Normal Text> </Normal Text><Integer>8</Integer><Normal Text>;</Normal Text><br/>
<Normal Text>        </Normal Text><Control>else</Control><br/>
<Normal Text>            </Normal Text><Control>if</Control><Normal Text> load_regs</Normal Text><Operator>=</Operator><Attribute>'1'</Attribute><Normal Text> </Normal Text><Control>then</Control><br/>
<Normal Text>                bit_ctr </Normal Text><Operator><=</Operator><Normal Text> </Normal Text><Integer>0</Integer><Normal Text>;</Normal Text><br/>
<Normal Text>            </Normal Text><Control>elsif</Control><Normal Text> bit_ctr </Normal Text><Operator>/=</Operator><Normal Text> </Normal Text><Integer>8</Integer><Normal Text> </Normal Text><Control>then</Control><br/>
<Normal Text>                bit_ctr </Normal Text><Operator><=</Operator><Normal Text> bit_ctr </Normal Text><Operator>+</Operator><Normal Text> </Normal Text><Integer>1</Integer><Normal Text>;</Normal Text><br/>
<Normal Text>            </Normal Text><Control>end if;</Control><br/>
<Normal Text>        </Normal Text><Control>end if;</Control><br/>
<Normal Text>    </Normal Text><Control>end if;</Control><br/>
<Process>end process control_counter</Process><Normal Text>;</Normal Text><br/>
<dsNormal></dsNormal><br/>
<Comment>-- Internal signal ready is asserted after 8 cycles.</Comment><br/>
<Comment>-- The sequential multiplier will use this signal too, IF it takes 8 cycles.</Comment><br/>
<dsNormal></dsNormal><br/>
<Normal Text>ready </Normal Text><Operator><=</Operator><Normal Text> </Normal Text><Attribute>'1'</Attribute><Normal Text> </Normal Text><Keyword>when</Keyword><Normal Text> bit_ctr </Normal Text><Operator>>=</Operator><Normal Text> </Normal Text><Integer>8</Integer><Normal Text> else </Normal Text><Attribute>'0'</Attribute><Normal Text>;</Normal Text><br/>
<dsNormal></dsNormal><br/>
<dsNormal></dsNormal><br/>
<Comment>---- Divider logic -------------------------------------------------------------</Comment><br/>
<dsNormal></dsNormal><br/>
<Comment>-- What we do is a simple base-2 'shift-and-subtract' algorithm that takes</Comment><br/>
<Comment>-- 8 cycles to complete. We can get away with this because we deal with unsigned</Comment><br/>
<Comment>-- numbers only.</Comment><br/>
<dsNormal></dsNormal><br/>
<Name>divider_registers</Name><Operator>:</Operator><Normal Text> </Normal Text><Process>process</Process><Normal Text>(clk)</Normal Text><br/>
<Process>begin</Process><br/>
<Normal Text>    </Normal Text><Control>if</Control><Normal Text> clk</Normal Text><Attribute>'event</Attribute><Normal Text> </Normal Text><Keyword>and</Keyword><Normal Text> clk</Normal Text><Operator>=</Operator><Attribute>'1'</Attribute><Normal Text> </Normal Text><Control>then</Control><br/>
<Normal Text>        </Normal Text><Comment>-- denominator shift register</Comment><br/>
<Normal Text>        </Normal Text><Control>if</Control><Normal Text> load_regs</Normal Text><Operator>=</Operator><Attribute>'1'</Attribute><Normal Text> </Normal Text><Control>then</Control><br/>
<Normal Text>            b_shift_reg </Normal Text><Operator><=</Operator><Normal Text> </Normal Text><Vector>"0"</Vector><Normal Text> </Normal Text><Operator>&</Operator><Normal Text> data_b </Normal Text><Operator>&</Operator><Normal Text> </Normal Text><Vector>"0000000"</Vector><Normal Text>;</Normal Text><br/>
<Normal Text>            </Normal Text><Comment>-- Division overflow can be determined upon loading B reg data.</Comment><br/>
<Normal Text>            </Normal Text><Comment>-- OV will be raised only on div-by-zero.</Comment><br/>
<Normal Text>            </Normal Text><Control>if</Control><Normal Text> data_b</Normal Text><Operator>=</Operator><Normal Text>X</Normal Text><Vector>"00"</Vector><Normal Text> </Normal Text><Control>then</Control><br/>
<Normal Text>                div_ov_out </Normal Text><Operator><=</Operator><Normal Text> </Normal Text><Attribute>'1'</Attribute><Normal Text>;</Normal Text><br/>
<Normal Text>            </Normal Text><Control>else</Control><br/>
<Normal Text>                div_ov_out </Normal Text><Operator><=</Operator><Normal Text> </Normal Text><Attribute>'0'</Attribute><Normal Text>;</Normal Text><br/>
<Normal Text>            </Normal Text><Control>end if;</Control><br/>
<Normal Text>        </Normal Text><Control>else</Control><br/>
<Normal Text>            b_shift_reg </Normal Text><Operator><=</Operator><Normal Text> </Normal Text><Vector>"0"</Vector><Normal Text> </Normal Text><Operator>&</Operator><Normal Text> b_shift_reg(b_shift_reg</Normal Text><Attribute>'high</Attribute><Normal Text> </Normal Text><Range>downto</Range><Normal Text> </Normal Text><Integer>1</Integer><Normal Text>);</Normal Text><br/>
<Normal Text>        </Normal Text><Control>end if;</Control><br/>
<Normal Text>        </Normal Text><br/>
<Normal Text>        </Normal Text><Comment>-- numerator register</Comment><br/>
<Normal Text>        </Normal Text><Control>if</Control><Normal Text> load_regs</Normal Text><Operator>=</Operator><Attribute>'1'</Attribute><Normal Text> </Normal Text><Control>then</Control><Normal Text> </Normal Text><br/>
<Normal Text>            rem_reg </Normal Text><Operator><=</Operator><Normal Text> data_a;</Normal Text><br/>
<Normal Text>        </Normal Text><Control>elsif</Control><Normal Text> bit_ctr</Normal Text><Operator>/=</Operator><Integer>8</Integer><Normal Text> </Normal Text><Keyword>and</Keyword><Normal Text> sub_num</Normal Text><Operator>=</Operator><Attribute>'1'</Attribute><Normal Text> </Normal Text><Control>then</Control><Normal Text> </Normal Text><br/>
<Normal Text>            rem_reg </Normal Text><Operator><=</Operator><Normal Text> rem_reg </Normal Text><Operator>-</Operator><Normal Text> denominator;</Normal Text><br/>
<Normal Text>        </Normal Text><Control>end if;</Control><br/>
<dsNormal></dsNormal><br/>
<Normal Text>        </Normal Text><Comment>--- quotient register</Comment><br/>
<Normal Text>        </Normal Text><Control>if</Control><Normal Text> load_regs</Normal Text><Operator>=</Operator><Attribute>'1'</Attribute><Normal Text> </Normal Text><Control>then</Control><br/>
<Normal Text>            quot_reg </Normal Text><Operator><=</Operator><Normal Text> (</Normal Text><Range>others</Range><Normal Text> </Normal Text><Operator>=></Operator><Normal Text> </Normal Text><Attribute>'0'</Attribute><Normal Text>);</Normal Text><br/>
<Normal Text>        </Normal Text><Control>elsif</Control><Normal Text> bit_ctr</Normal Text><Operator>/=</Operator><Integer>8</Integer><Normal Text> </Normal Text><Control>then</Control><br/>
<Normal Text>            quot_reg </Normal Text><Operator><=</Operator><Normal Text> quot_reg(quot_reg</Normal Text><Attribute>'high-1</Attribute><Normal Text> </Normal Text><Range>downto</Range><Normal Text> </Normal Text><Integer>0</Integer><Normal Text>) </Normal Text><Operator>&</Operator><Normal Text> sub_num;</Normal Text><br/>
<Normal Text>        </Normal Text><Control>end if;</Control><br/>
<Normal Text>        </Normal Text><br/>
<Normal Text>        load_regs </Normal Text><Operator><=</Operator><Normal Text> start;</Normal Text><br/>
<Normal Text>    </Normal Text><Control>end if;</Control><br/>
<Process>end process divider_registers</Process><Normal Text>;</Normal Text><br/>
<dsNormal></dsNormal><br/>
<Normal Text>denominator </Normal Text><Operator><=</Operator><Normal Text> b_shift_reg(</Normal Text><Integer>7</Integer><Normal Text> </Normal Text><Range>downto</Range><Normal Text> </Normal Text><Integer>0</Integer><Normal Text>);</Normal Text><br/>
<dsNormal></dsNormal><br/>
<Comment>-- The 16-bit comparison between b_shift_reg (denominator) and the zero-extended </Comment><br/>
<Comment>-- rem_reg (numerator) can be simplified by splitting it in 2: </Comment><br/>
<Comment>-- If the shifted denominator high byte is not zero, it is >=256...</Comment><br/>
<Normal Text>den_ge_256 </Normal Text><Operator><=</Operator><Normal Text> </Normal Text><Attribute>'1'</Attribute><Normal Text> </Normal Text><Keyword>when</Keyword><Normal Text> b_shift_reg(</Normal Text><Integer>15</Integer><Normal Text> </Normal Text><Range>downto</Range><Normal Text> </Normal Text><Integer>8</Integer><Normal Text>) </Normal Text><Operator>/=</Operator><Normal Text> X</Normal Text><Vector>"00"</Vector><Normal Text> else </Normal Text><Attribute>'0'</Attribute><Normal Text>;</Normal Text><br/>
<Comment>-- ...otherwise we need to compare the low bytes.</Comment><br/>
<Normal Text>num_ge_den </Normal Text><Operator><=</Operator><Normal Text> </Normal Text><Attribute>'1'</Attribute><Normal Text> </Normal Text><Keyword>when</Keyword><Normal Text> rem_reg </Normal Text><Operator>>=</Operator><Normal Text> denominator else </Normal Text><Attribute>'0'</Attribute><Normal Text>;</Normal Text><br/>
<Normal Text>sub_num </Normal Text><Operator><=</Operator><Normal Text> </Normal Text><Attribute>'1'</Attribute><Normal Text> </Normal Text><Keyword>when</Keyword><Normal Text> den_ge_256</Normal Text><Operator>=</Operator><Attribute>'0'</Attribute><Normal Text> </Normal Text><Keyword>and</Keyword><Normal Text> num_ge_den</Normal Text><Operator>=</Operator><Attribute>'1'</Attribute><Normal Text> else </Normal Text><Attribute>'0'</Attribute><Normal Text>;</Normal Text><br/>
<dsNormal></dsNormal><br/>
<dsNormal></dsNormal><br/>
<Normal Text>quot_out </Normal Text><Operator><=</Operator><Normal Text> quot_reg;</Normal Text><br/>
<Normal Text>prod_out </Normal Text><Operator><=</Operator><Normal Text> prod_reg;</Normal Text><br/>
<Normal Text>rem_out </Normal Text><Operator><=</Operator><Normal Text> rem_reg;</Normal Text><br/>
<dsNormal></dsNormal><br/>
<Normal Text>div_ready </Normal Text><Operator><=</Operator><Normal Text> ready;</Normal Text><br/>
<dsNormal></dsNormal><br/>
<Comment>---- Multiplier logic ----------------------------------------------------------</Comment><br/>
<dsNormal></dsNormal><br/>
<Comment>---- Combinational multiplier -----------------------------</Comment><br/>
<Name>multiplier_combinational</Name><Operator>:</Operator><Normal Text> </Normal Text><Control>if</Control><Normal Text> </Normal Text><Keyword>not</Keyword><Normal Text> SEQUENTIAL_MULTIPLIER </Normal Text><Control>generate</Control><br/>
<dsNormal></dsNormal><br/>
<Name>registered_combinational_multiplier</Name><Operator>:</Operator><Process>process</Process><Normal Text>(clk)</Normal Text><br/>
<Process>begin</Process><br/>
<Normal Text>    </Normal Text><Control>if</Control><Normal Text> clk</Normal Text><Attribute>'event</Attribute><Normal Text> </Normal Text><Keyword>and</Keyword><Normal Text> clk</Normal Text><Operator>=</Operator><Attribute>'1'</Attribute><Normal Text> </Normal Text><Control>then</Control><br/>
<Normal Text>        prod_reg </Normal Text><Operator><=</Operator><Normal Text> data_a </Normal Text><Operator>*</Operator><Normal Text> data_b; </Normal Text><Comment>-- t_byte is unsigned</Comment><br/>
<Normal Text>    </Normal Text><Control>end if;</Control><br/>
<Process>end process registered_combinational_multiplier</Process><Normal Text>;</Normal Text><br/>
<dsNormal></dsNormal><br/>
<Comment>-- The multiplier output is valid in the cycle after the operands are loaded,</Comment><br/>
<Comment>-- so by the time MUL is executed it's already done.</Comment><br/>
<Normal Text>mul_ready </Normal Text><Operator><=</Operator><Normal Text> </Normal Text><Attribute>'1'</Attribute><Normal Text>;</Normal Text><br/>
<dsNormal></dsNormal><br/>
<Normal Text>mul_ov_out </Normal Text><Operator><=</Operator><Normal Text> </Normal Text><Attribute>'1'</Attribute><Normal Text> </Normal Text><Keyword>when</Keyword><Normal Text> prod_reg(</Normal Text><Integer>15</Integer><Normal Text> </Normal Text><Range>downto</Range><Normal Text> </Normal Text><Integer>8</Integer><Normal Text>)</Normal Text><Operator>/=</Operator><Normal Text>X</Normal Text><Vector>"00"</Vector><Normal Text> else </Normal Text><Attribute>'0'</Attribute><Normal Text>;</Normal Text><br/>
<Normal Text>prod_out </Normal Text><Operator><=</Operator><Normal Text> prod_reg;</Normal Text><br/>
<dsNormal></dsNormal><br/>
<Control>end generate multiplier_combinational</Control><Normal Text>;</Normal Text><br/>
<dsNormal></dsNormal><br/>
<Comment>---- Sequential multiplier --------------------------------</Comment><br/>
<Name>multiplier_sequential</Name><Operator>:</Operator><Normal Text> </Normal Text><Control>if</Control><Normal Text> SEQUENTIAL_MULTIPLIER </Normal Text><Control>generate</Control><br/>
<dsNormal></dsNormal><br/>
<Keyword>assert</Keyword><Normal Text> false</Normal Text><br/>
<Keyword>report</Keyword><Normal Text> </Normal Text><Vector>"Sequential multiplier implementation not done yet."</Vector><Operator>&</Operator><br/>
<Normal Text>       </Normal Text><Vector>" Use combinational implementation."</Vector><br/>
<Keyword>severity</Keyword><Normal Text> </Normal Text><Keyword>failure</Keyword><Normal Text>;</Normal Text><br/>
<dsNormal></dsNormal><br/>
<Control>end generate multiplier_sequential</Control><Normal Text>;</Normal Text><br/>
<dsNormal></dsNormal><br/>
<Control>end sequential;</Control><br/>
